A Survey of Lifetime Reliability-Aware System-Level Design Techniques for Embedded Multiprocessor Systems

Lifetime reliability is emerging as a major concern for system design as escalating power density and hence temperature variation continues to accelerate wear-out, leading to a growing prominence of device-defects. This has attracted a significant attention both in industry and in academia to investigate on wear-out mitigation techniques, from micro-architectural adaptations to systemlevel optimization. Task mapping and scheduling-based system-level design techniques provide a low overhead approach for reliability optimization at design-time as well as reliability management at run-time. This paper provides an overview of the developments on reliability optimization using task mapping and scheduling over the past decade, since the introduction of the first reliability-aware system-level design technique in 2004.